When configuration data, to configure a circuit which can execute a predetermined processing, is set or written to an integrated circuit in which a plurality of logic circuit elements, memory circuit elements, wires, switches and the like are formed in advance, a programmable logic device (hereafter PLD) reconfigures the circuit which can execute the predetermined processing. This PLD is, for example, a field programmable gate array (FPGA), and is an LSI which can reconfigure internal circuits into various logic circuits by overwriting the configuration data. The PLD will now be described using an FPGA as an example.
To execute a predetermined software processing (e.g. job) using a dedicated hardware circuit, the processor configures a dedicated circuit in the FPGA by setting or writing the configuration data to configure the dedicated circuit to the FPGA, so that the dedicated circuit executes the predetermined processing. When the dedicated circuit ends the predetermined processing, the processor configures another dedicated circuit to execute a different processing in the FPGA by setting or writing the configuration data of this dedicated circuit to the FPGA, so that this dedicated circuit executes the different processing. By the processor causing a dedicated circuit of the FPGA to execute a predetermined software processing, so that the FPGA is used as an accelerator of the processor. Thereby the power of the information processing apparatus (computer) including the processor can be saved, and the functions thereof can be improved.
As the scale of the FPGA increases, a plurality of logic circuits can now be configured in the FPGA, and the plurality of logic circuits can be operated in parallel. Further, a plurality of logic circuits can be asynchronously and dynamically reconfigured and operated asynchronously in parallel, such as reconfiguring a part of the logic circuit and starting the operation of new logic circuits while running a plurality of logic circuits configured in the FPGA.
Configuring a plurality of circuits in an FPGA is disclosed in Japanese Laid-open Patent Publication No. 2015-154417, No. 2004-32043, No. 2016-76867 and No. 2015-231205, and Japanese Patent Application No. 2016-248297. Japanese Patent Application No. 2016-248297 is an application, but is not a publically known example.